In a conventional LSI, elements are integrated in a two-dimensional plane on a silicon substrate. To increase the storage capacity of a memory, therefore, the dimensions of each element must be decreased (by micropatterning). Recently, however, this micropatterning has become difficult from the viewpoints of cost and technique.
The micropatterning of elements requires improvements in photolithography techniques. In the present ArF immersion exposure technique, rules near 40 nm are the resolution limits, and it is necessary to introduce an EUV (Extreme Ultra Violet) exposure device in order to further advance micropatterning. However, the EUV exposure device requires a very high cost and hence is impractical. Also, even if micropatterning is achieved, the breakdown voltage between elements or the like presumably reaches the physical critical point unless the driving voltage or the like is scaled. This increases the possibility that the operation of the device becomes difficult.
To solve the above problem, a method of three-dimensionally stacking memories has been proposed. However, a general three-dimensional device requires a lithography step to be performed at least three times for each layer, and this lithography step requires a high cost. That is, the three-dimensional memory can increase the storage capacity but cannot reduce the cost. On the contrary, the cost becomes higher than that of a regular two-dimensional memory if four or more layers are stacked.
To solve the cost problem posed by the three-dimensional memory as described above, a BiCS (Bit-Coast Scalable) memory has been proposed. This manufacturing method can collectively form a three-dimensional multilayered memory regardless of the number of layers to be stacked. Therefore, the increase in cost can be suppressed. In the BiCS memory, MONOS transistors are arranged as memory cells at the intersections of gate electrodes and silicon pillars.
As this BiCS memory, a pipe-shaped NAND flash memory in which U-shaped NAND strings are formed in the stacking direction has been proposed. In this pipe-shaped NAND flash memory, two adjacent silicon pillars form one NAND string. More specifically, select gates are formed on the upper ends of the two silicon pillars, one select gate is connected to a bit line, and the other is connected to a source line. Also, the lower ends of the two adjacent silicon pillars are connected by a transistor called a pipe.
To further reduce the area (i.e., to further advance the micropatterning) of the pipe-shaped BiCS memory, a power supply circuit such as a charge pump, a peripheral circuit, a control circuit, and the like can be embedded below a cell array.
In this structure, however, when a data read or write signal passes through the pipe portion formed in the lowermost layer of the cell array, the charge pump in the lower portion is driven and gives noise to the signal. This may cause a write error or read error.